Method of manufacturing semiconductor package

ABSTRACT

A method of manufacturing a semiconductor package, the method including: disposing a plurality of semiconductor chips; forming a sealing part sealing the plurality of semiconductor chips; forming a substrate part on at least one surface of the sealing part; and forming an antenna part on the sealing part or the substrate part.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a U.S. divisional application filed under 37 CFR1.53(b) claiming priority benefit of U.S. Ser. No. 13/200,335 filed inthe United States on Sep. 23, 2011, which claims earlier foreignpriority benefit to Korean Patent Application No. 10-2011-0067437 filedwith the Korean Intellectual Property Office on Jul. 7, 2011, thedisclosures of which are incorporated herein by reference.

BACKGROUND

1. Field

The present invention relates to a semiconductor package and a method ofmanufacturing the same, and more particularly, to a semiconductorpackage including an antenna formed integrally therewith, and a methodof manufacturing the same.

2. Description of the Related Art

As a frequency resource for a next generation information communicationservice, a frequency in the millimeter wave band, a super high frequencyband of 30 GHz or more, has been actively studied.

This frequency in the millimeter wave band has advantages in that alarge amount of information may be transferred at high speed usingwideband characteristics and that the frequency may be re-used, that is,a band having the same frequency may be used without interference in anadjacent geographical area due to significant electrical waveattenuation in the air. Therefore, many researchers have been interestedin the frequency in the millimeter wave band.

As a result, the development of an information communication service andsystem using the frequency in the millimeter wave as well as researchinto, and development of, various components required for theinformation communication service and system have been conducted.

In this millimeter wave band, an electrical connection distance betweenan antenna and a semiconductor chip is very important. That is, when adistance between the antenna and the semiconductor chip increases, lossincreases. Therefore, an antenna in the millimeter wave band(particularly, the 60 GHz band) may be electrically connected to thesemiconductor chip to be close thereto.

To this end, according to the related art, an antenna is disposed at aposition significantly adjacent to a semiconductor package in which asemiconductor chip is embedded, and the antenna and the semiconductorpackage are electrically connected to each other at the shortestpossible distance.

In the case of the related art, after the semiconductor package and theantenna are separately manufactured, they are mounted on a substrate andelectrical connections are made. Therefore, a manufacturing process iscomplicated.

Accordingly, the demand for a structure in which an antenna and asemiconductor package are disposed at a closer distance to one other hasincreased. In addition, the necessity for a manufacturing method capableof simplifying a process has increased.

SUMMARY

An aspect of the present invention provides a semiconductor packagecapable of being easily manufactured while minimizing an electricalconnection distance between an antenna and a semiconductor chip.

Another aspect of the present invention provides a method ofmanufacturing a semiconductor package through a simplified semiconductormanufacturing process.

Another aspect of the present invention provides a method ofmanufacturing a semiconductor package capable of producing a compact andthin semiconductor package through a semiconductor manufacturingprocess.

According to an aspect of the present invention, there is provided asemiconductor package including: a semiconductor chip; a sealing partsealing the semiconductor chip; a substrate part formed on at least onesurface of the sealing part; and an antenna part formed on the sealingpart or the substrate part and electrically connected to thesemiconductor chip.

The semiconductor package may further include a via connection partpenetrating through the sealing part, and the antenna part and thesemiconductor chip may be electrically connected to each other throughthe via connection part.

The substrate part may include an upper substrate formed on an uppersurface of the sealing part, and a lower substrate formed on a lowersurface of the sealing part.

The antenna part may be formed on an outer surface of the uppersubstrate.

The upper substrate may be a multi-layer substrate, and the antenna partmay include a plurality of radiators formed on several layers of theupper substrate.

The antenna part may be formed on an outer surface of the sealing part.

The antenna part may be formed in a groove formed in the outer surfaceof the sealing part.

The substrate part may have fine circuit patterns formed in an innerportion thereof through a semiconductor manufacturing process.

The semiconductor chip may transceive a high frequency in a millimeterwave band through the antenna part.

According to another aspect of the present invention, there is provideda method of manufacturing a semiconductor package, the method including:disposing a plurality of semiconductor chips; forming a sealing partsealing the plurality of semiconductor chips; forming a substrate parton at least one surface of the sealing part; and forming an antenna parton the sealing part or the substrate part.

The disposing of the plurality of semiconductor chips may includearranging semiconductor chips sorted into good products on a carrier.

The disposing of the plurality of semiconductor chips may includeattaching the semiconductor chips to an adhesive layer formed on thecarrier.

The forming of the sealing part may include forming the sealing partusing an epoxy mold compound (EMC).

The method may further include, after the forming of the sealing part,forming a via connection part penetrating through the sealing part.

The forming of the antenna part may include electrically connecting theantenna part and the semiconductor chips through the via connectionpart.

The forming of the substrate part may include forming a multi-layersubstrate part on each of upper and lower surfaces of the sealing part.

The forming of the antenna part may include forming a plurality ofradiators on several layers of the substrate part.

The forming of the antenna part may include forming a groove in an outersurface of the sealing part and forming the antenna part therein.

The forming of the substrate part may include repeatedly forming finecircuit patterns and insulating layers through a semiconductormanufacturing process.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and other advantages of thepresent invention will be more clearly understood from the followingdetailed description taken in conjunction with the accompanyingdrawings, in which:

FIG. 1 is a perspective view schematically showing a semiconductorpackage according to an embodiment of the present invention;

FIG. 2 is a cross-sectional view taken along line A-A′ of thesemiconductor package shown in FIG. 1;

FIGS. 3A through 3I are views describing a method of manufacturing asemiconductor package according to an embodiment of the presentinvention;

FIG. 4 is a flowchart showing a method of manufacturing a semiconductorpackage according to an embodiment of the present invention; and

FIGS. 5 and 6 are cross-sectional views schematically showing asemiconductor package according to other embodiments of the presentinvention.

DESCRIPTION OF EMBODIMENTS

Prior to a detailed description of the present invention, the terms orwords, which are used in the specification and claims to be describedbelow, should not be construed as having typical or dictionary meanings.The terms or words should be construed in conformity with the technicalidea of the present invention on the basis of the principle that theinventor(s) can appropriately define terms in order to describe his orher invention in the best way. Embodiments described in thespecification and structures illustrated in drawings are merelyexemplary embodiments of the present invention. Thus, it is intendedthat the present invention covers the modifications and variations ofthis invention, provided they fall within the scope of their equivalentsat the time of filing this application.

Exemplary embodiments of the present invention will be described indetail with reference to the accompanying drawings. The same referencenumerals will be used throughout to designate the same or like elementsin the accompanying drawings. Moreover, detailed descriptions related towell-known functions or configurations will be ruled out in order not tounnecessarily obscure subject matters of the present invention. In thedrawings, the shapes and dimensions of some elements may be exaggerated,omitted or schematically illustrated. Also, the size of each elementdoes not entirely reflect an actual size.

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings.

FIG. 1 is a perspective view schematically showing a semiconductorpackage according to an embodiment of the present invention, and FIG. 2is a cross-sectional view taken along line A-A′ of the semiconductorpackage shown in FIG. 1.

As shown in FIGS. 1 and 2, a semiconductor package 100 according to thepresent embodiment includes a semiconductor chip 10, a sealing part 20sealing the semiconductor chip 10, a substrate part 30 disposed on bothsurfaces of the sealing part 20, and an antenna part 40.

The semiconductor chip 10 includes a plurality of connection pads 12 forconnecting to the outside and is electrically connected to the substratepart 30 and the antenna part 40 (to be described below) through theconnection pads 12. The connection pads 12 may have the form of a solderbump. However, the present invention is not limited thereto but may bevariously applied. For example, the connection pads 12 may have the formof a pad for wire bonding.

This semiconductor chip 10 may perform wireless communications with theoutside through the antenna part 40.

The sealing part 20 encloses the entire semiconductor chip 10 such thatthe semiconductor chip 10 is embedded therein, thereby sealing thesemiconductor chip 10. That is, the sealing part 20 encloses an outerportion of the semiconductor chip 10 and fixes the semiconductor chip 10to the substrate part 30, thereby securely protecting the semiconductorchip 10 from external impacts.

As a method of forming the sealing part 20, a molding method may beused. In this case, an epoxy mold compound (EMC) may be used as amaterial of the sealing part 20. However, the present invention is notlimited thereto. That is, various methods such as a printing method, aspin coating method, a jetting method, and the like, may be used forforming the sealing part 20 as necessary.

The substrate part 30 may be formed on at least one surface of thesealing part 20 having the semiconductor chip 10 embedded therein. Thepresent embodiment describes a case in which the substrate part 30includes each of upper and lower substrates 30 a and 30 b formed on bothsurfaces (upper and lower surfaces) of the sealing part 20 by way ofexample. As the substrate part 30, various kinds of substrates (forexample, a silicon substrate, a ceramic substrate, a printed circuitboard (PCB), a flexible substrate, a circuit pattern layer by asemiconductor circuit process, and the like) known in the art may beused.

Electrode patterns 32 electrically connected to the semiconductor chip10 and circuit patterns 36 electrically connecting the electrodepatterns 32 to each other may be formed on one surface of the substratepart 30, that is, a bonding surface between the substrate part 30 andthe sealing part 20.

In addition, the substrate part 30 according to the present embodimentmay be a multi-layer substrate configured of a plurality of layers. Thecircuit patterns 36 for forming an electrical connection may be formedbetween the respective layers. The substrate part 30 may have externalelectrodes 38 formed on an outer surface thereof, and the externalelectrodes 38 electrically connect the semiconductor package 100 to theoutside.

In addition, the substrate part 30 according to the present embodimentmay include the external electrodes 38, the electrode patterns 32 andconductive vias 34 electrically connecting the circuit patterns 36 toeach other.

Here, the substrate part 30 according to the present embodiment may beformed through a semiconductor manufacturing process. Therefore, theexternal electrode 38, the electrode pattern 32, the circuit pattern 36,the conductive via 34, and the like, formed in the substrate part 30 maybe formed as fine circuit patterns by the semiconductor manufacturingprocess.

The antenna part 40 is formed by disposing a radiator on the outersurface of the substrate part 30, that is, a top portion. The form ofthe radiator may be varied, having a liner, polygonal, circular, orother shape, and may be a dipole or monopole form.

The antenna part 40 according to the present embodiment may be formed tohave a single radiator or be formed by complexly disposing a pluralityof radiators on several layers as necessary. FIG. 2 shows a case inwhich the radiators are formed in parallel with each other on the outersurface of the substrate part 30 and an inner portion of the substratepart 30.

In addition, the antenna part 40 may be electrically connected to thesemiconductor chip 10 through the circuit pattern 36, the via 34, a viaconnection part 25, and the like.

Meanwhile, although the present embodiment describes a case in which theantenna part 40 is formed in the upper substrate 30 a by way of example,the present invention is not limited thereto. That is, the antenna part40 may also be disposed on an outer surface of the lower substrate 30 b,that is, a bottom surface of the lower substrate 30 b in order tominimize an electrical connection distance between the antenna part 40and the semiconductor chip 10.

In the case of the semiconductor package 100 configured as describedabove, the antenna part 40 is formed on the outer surface of thesubstrate part 30 and an electrical connection distance between theantenna part 40 and the semiconductor chip 10 is significantly short,whereby radiation characteristics and electrical loss of the antennapart 40 may be improved.

Next, a method of manufacturing a semiconductor package according to anembodiment of the present invention will be described.

FIGS. 3A through 3I are views describing a method of manufacturing asemiconductor package according to an embodiment of the presentinvention; and FIG. 4 is a flowchart showing a method of manufacturing asemiconductor package according to an embodiment of the presentinvention.

With reference to FIGS. 3A through 4, a method of manufacturing asemiconductor package according to an embodiment of the presentinvention in initiated in preparing the semiconductor chip 10 inoperation S10.

A plurality of semiconductor chips formed on a wafer may be cut intoindividual chips through a known semiconductor manufacturing process andthen the individual chips may be sorted into a good product or a badproduct.

Then, as shown in FIGS. 3A and 3B, the plurality of semiconductor chips10 are disposed in operation S11. Here, FIG. 3B shows a cross-sectionalview taken along line B-B′ of FIG. 3A.

The semiconductor chips 10 may be disposed such that they are uniformlyarranged on a carrier 60 having various shapes.

The carrier 60 includes an adhesive layer 70 formed on one surfacethereof, and the semiconductor chips 10 are mounted on the adhesivelayer 70. Here, the semiconductor chips 10 are mounted such that activeareas thereof having the connection pads 12 formed therein may beattached to the adhesive layer 70 of the carrier 60.

The adhesive layer 70 may have adhesion changed by light or heat. As anexample, adhesive tape may be used. However, the present invention isnot limited thereto but may be variously applied. The adhesive layer 70may be formed by applying an adhesive resin, or the like, to one surfaceof the carrier 60.

The carrier 60 may be formed of a flat, hard wafer disk. However, thisconfiguration in which the carrier 60 uses the wafer was deduced becausethe method of manufacturing the semiconductor package 100 according tothe present embodiment utilizes a semiconductor manufacturing processusing a wafer. Therefore, the carrier 60 according to the presentembodiment is not limited to having a circular shape but may bevariously shaped according to embodiments of the semiconductormanufacturing process. Although FIG. 3A shows a good chip carrier havingthe circular shape, the carrier 60 may have various forms including arectangular substrate.

After the plurality of semiconductor chips 10 are mounted on the carrier60, the sealing part 20 is formed in operation S12 as shown in FIG. 3C.

The sealing part 20 according to the present embodiment covers theentire carrier 60. That is, the sealing part 20 fills spaces between theindividual semiconductor chips 10. Therefore, when the forming of thesealing part 20 is completed, all of the semiconductor chips 10 areformed integrally with each other by the sealing part 20.

After the carrier 60 on which the semiconductor chips 10 are mounted isdisposed within a mold (not shown), the sealing part 20 according to thepresent embodiment may be formed by injecting a mold resin into the moldand hardening it.

Next, as shown in FIG. 3D, one surface of the sealing part 20 is groundusing a grinder 50 in operation S13. Therefore, an unnecessary portionof the sealing part 20 is removed, whereby the thickness of thesemiconductor package 100 may be reduced.

In addition, in the semiconductor package 100 according to the presentembodiment, a distance between the antenna part 40 and the semiconductorchips 10, permittivity according to the distance, and the like, may beadjusted through the grinding of the sealing part 20. Therefore,characteristics of the antenna part 40, that is, signal matchingcharacteristics may be optimally adjusted through this operation S13.

Accordingly, the unnecessary portion of the sealing part 20 may beremoved corresponding to optimal signal matching.

Meanwhile, when the adjustment of a thickness of the sealing part 20 orsignal matching is not required to be performed, this operation may beomitted.

Thereafter, as shown in FIG. 3E, the removing of the adhesive layer 70is performed in operation S14. This may be easily undertaken by applyingheat to the adhesive layer 70 or irradiating the adhesive layer 70 withlight to weaken the adhesion thereof. The adhesive layer 70, attached tothe other surface of the sealing part 20, is removed, such that theconnection pads 12 of the semiconductor chips 10 that have been attachedto the adhesive layer 70 are exposed to the outside on the other surfaceof the sealing part 20.

Meanwhile, a lower surface of the sealing part 20 in which the adhesivelayer is removed may be continuously supported by the carrier 60.However, hereinafter, for convenience of description, the carrier 60 maybe omitted in the drawings.

Then, at least one substrate part 30 may be formed on any one surface ofthe sealing part 20. The present embodiment describes a case in whichthe lower substrate 30 b is first formed in operation S15 by way ofexample as shown in FIG. 3F.

The sealing part 20 is disposed in a form in which upper and lowersurfaces thereof are inverted. That is, the sealing part 20 is mountedon the carrier such that the connection pad 12 of the semiconductor chip10 is exposed upwardly.

The lower substrate 30 b may be formed by repeatedly performing aprocess of forming the circuit patterns 36, the electrode patterns 32,or the like, on the upper surface of the sealing part 20, on which theconnection pad 12 is exposed, and forming an insulating layer 31 thereonagain. At this time, the electrode patterns 32 or the circuit patterns36 may be formed to be electrically connected to the connection pads 12exposed on the sealing part 20.

In addition, the vias 34 penetrating through the insulating layers 31may be formed as necessary to thereby electrically connect therespective insulating layers 31, and the external electrodes 38 forconnection to the outside may be formed on an outer surface of theinsulating layer 31.

Here, as a method of forming the circuit pattern 36, the insulatinglayer 31, the via 34, or the like, a semiconductor manufacturing processknown in the art, or the like, may be used. Therefore, a detaileddescription thereof will be omitted.

When the substrate part 30 is formed using the semiconductormanufacturing process as in the present embodiment, fine circuitpatterns may be formed on the substrate part 30. In addition, thesubstrate part may have a significantly reduced thickness as compared toa general printed circuit board (PCB). Therefore, the semiconductor chip100 according to the present embodiment may be a chip scale package(CSP).

After the lower substrate 30 b is formed, the via connection part 25penetrating through the sealing part 20 is formed in operation S16 asshown in FIG. 3G. At this time, the via connection part 25 is formed ata position corresponding to that of the circuit pattern 36 formed on thelower substrate 30 b. Therefore, the via connection part 25 may beelectrically connected to the semiconductor chip 10 through the circuitpattern 36.

The via connection part 25 may be formed by drilling a through hole 23in the sealing part 20, so that the circuit pattern 36 of the lowersubstrate 30 b is exposed, filling the through hole 23 with a conductivematerial (for example, copper, solder, or the like) and hardening theconductive material. The through hole 23 may be formed using a methodsuch as laser drilling. However, the through hole 23 is not limited tobeing formed using laser drilling, but may also be formed using othermethods as required.

Meanwhile, the present embodiment describes a case in which the viaconnection part 25 is formed after the forming of the lower substrate 30b by way of example. However, the present invention is not limitedthereto. That is, after the sealing part 20 is formed in operation S12or S13, the via connection part 25 is first formed in the sealing part20 before the forming of the lower substrate 30 b.

Next, as shown in FIG. 3H, the upper substrate 30 a is formed on onesurface of the sealing part 20 in operation S17. The upper substrate 30a may be formed to have a shape similar to that of the above-mentionedlower substrate 30 b through the same process as that of forming thelower substrate 30 b.

First, the sealing part 20 is reinverted such that the connection pad 12of the semiconductor chip 10 is directed downwardly. Then, the uppersubstrate 30 a may be formed by repeatedly performing a process offorming the circuit patterns 36, the electrode patterns 32, or the like,on the upper surface of the sealing part 20 and forming the insulatinglayer 31 thereon again.

In this operation, the antenna part 40 may be formed on the uppersubstrate 30 a.

The antenna part 40 may have the form of the circuit pattern 36 in aprocess of forming the circuit pattern 36 of the upper substrate 30 a.In addition, the antenna part 40 may be electrically connected to thesemiconductor chip 10 through the via 34 formed in the upper substrate30 a, the via connection part 25 formed in the sealing part 20, or thelike.

Since the antenna part 40 as well as the substrate part 30 may be formedduring the process of forming the substrate part 30 as described above,a manufacturing process may be facilitated as compared to the case ofthe related art in which the antenna part 40 is separately manufacturedand then coupled to the substrate part 30.

Further, in the antenna part 40 according to the present embodiment, atleast one radiator may have the form of the circuit pattern 36 in theinner portion of the upper substrate 30 a as well as on the outersurface of the upper substrate 30 a in order to secure radiationcharacteristics and impedance bandwidth required for wirelesscommunications.

After the upper substrate 30 a is formed, the individual semiconductorpackages 100 are formed in operation S18 as shown in FIG. 3I. Thesemiconductor chips 10 are separated by being cut therebetween using acutting blade 80, a laser beam, or the like, such that the semiconductorchips 10 formed integrally by the sealing part 20 are individuallyseparated. As a result, the individual semiconductor packages 100 asshown in FIG. 1 are formed.

With the semiconductor package and the method of manufacturing the sameaccording to the present embodiment configured as described above, onlygood semiconductor chips are sorted from the individual semiconductorchips 10 and are rearranged to manufacture the semiconductor package,whereby reliability may be secured.

In addition, the substrate part 30 formed on both surfaces (that is,upper and lower surfaces) of the semiconductor package 100 is utilized,whereby the semiconductor package may be miniaturized and system inpackage may be implemented.

Further, the sealing of the semiconductor chip 10 is used to therebyprotect the semiconductor chip 10 from the outside, whereby thesemiconductor chips 10 having various forms such as a flip chip, a chipusing a wire bonding scheme, or the like, may be utilized.

Furthermore, in the semiconductor package 100 according to the presentembodiment, the antenna part 40 and the semiconductor chip 10 aredisposed adjacent to each other to be formed integrally, whereby anelectrical connection distance between the semiconductor chip 10 and theantenna part 40 may be minimized. Therefore, when the semiconductorpackage 100 according to the present embodiment is used in themillimeter wave band (particularly, 60 GHz band), loss generated betweenthe antenna part 40 and the semiconductor chip 10 may be minimized.

In addition, the method of manufacturing a semiconductor packageaccording to the present embodiment forms the antenna part 40 during theprocess of forming the substrate part 30, whereby the number ofmanufacturing processes and a manufacturing costs may be reduced ascompared to the case of the related art in which the antenna part isseparately manufactured and then coupled to the substrate part.

Further, the method of manufacturing a semiconductor package accordingto the present embodiment uses a semiconductor manufacturing process.Therefore, the semiconductor manufacturing equipment according to therelated art may be utilized, whereby a requirement for investment in newequipment for manufacturing the semiconductor package may be minimized.In addition, fine circuit patterns are formed on a substrate through thesemiconductor manufacturing process, whereby the semiconductor package100 may be miniaturized and thinned. Further, a general semiconductormanufacturing process is utilized, whereby the semiconductor package maybe easily manufactured.

In addition, a sealing technology having high reliability is used,whereby reliability for packaging of the semiconductor chip 10 may besecured.

Furthermore, the sealing part 20 is ground to adjust a thickness thereofand the antenna part 40 is then formed, whereby characteristics of theantenna part 40 may be adjusted. Therefore, the signal matching of theantenna part 40 may be performed during a manufacturing process.

Meanwhile, although the present embodiment describes the substrate part30 as being formed on both surfaces with respect to a singlesemiconductor chip 10, the present invention is not limited thereto. Inthe case in which a plurality of semiconductor chips 10 are embeddedsuch as the case in which the semiconductor chips 10 are stacked, or thelike, a ratio of a system in package may be increased.

The semiconductor package and the method of manufacturing the sameaccording to the present invention may be variously applied.

FIGS. 5 and 6 are cross-sectional views schematically showing asemiconductor package according to other embodiments of the presentinvention.

First, referring to FIG. 5, a semiconductor package 200 according to thepresent embodiment is different from the semiconductor package 100according to the above-mentioned embodiment in terms of a configurationin which a plurality of semiconductor chips 10 and 11 are mounted whilebeing stacked, a configuration in which the semiconductor chip 10 iselectrically connected to the substrate part 30 through a wire bondingscheme, and a configuration in which the antenna part 40 is directlyformed on the sealing part 20 rather than the upper substrate 30 a (SeeFIG. 2).

Particularly, in the semiconductor package 200 according to the presentembodiment, after the thickness of the sealing part 20 may be adjustedusing a grinder, or the like, and a groove 27 may be formed using alaser beam, or the like, a radiator of the antenna part 40 may be thenformed to have a circuit pattern form in the groove 27.

Meanwhile, when a depth of the groove 27 is variously formed using thelaser beam, or the like, and the antenna part 40 is then formed in aninner portion of the groove 27 as shown in FIG. 5, the radiator of theantenna part 40 may have various thicknesses.

The above-mentioned configuration may be realized by adding the formingof the groove 27 in one surface of the sealing part 20. The forming ofthe groove 27 may be undertaken after operation S13 of grinding onesurface of the sealing part 20 as described above or may be performedwithout operation S13.

As described above, the semiconductor package 200 according to thepresent embodiment may utilize the semiconductor chips 10 having variousshapes, and the substrate part 30 having various shapes.

In the case in which the antenna part 40 is formed as described above,the depth of the groove 27 in which the antenna part 40 is formed isadjusted, whereby characteristics of the antenna part 40 may beadjusted.

However, the present invention is not limited thereto. For example, theantenna part 40 may also be formed without forming the groove 27 in thesealing part 20. In this case, the number of manufacturing processes maybe reduced.

Referring to FIG. 6, a semiconductor package 300 according to thepresent embodiment is different from the semiconductor package 100 (SeeFIG. 2) according to the above-mentioned embodiment only in that anactive area of the semiconductor chip 10 in which the connection pad 12is formed is disposed to face the upper substrate 30 a. In the case inwhich the semiconductor package 300 is configured as described above, anelectrical distance between the semiconductor chip 10 and the antennapart 40 is shorter than that of the above-mentioned semiconductorpackage 100 shown in FIG. 2.

In addition, the via connection part 25 that has been used toelectrically connect the semiconductor chip 10 and the antenna part 40to each other is not used, whereby electrical loss may be furtherreduced.

The semiconductor package and the method of manufacturing the sameaccording to the present invention as described above are not limited tothe above-mentioned embodiments but may be variously applied. Forexample, although the above-mentioned embodiments describe a case inwhich the substrate part is formed through the semiconductormanufacturing process by way of example, various methods may be appliedthereto. For example, the substrate part may also be formed using ageneral method of manufacturing a printed circuit board.

In addition, although the above-mentioned embodiments describe a case inwhich the semiconductor package is manufactured by disposing thesemiconductor chips on the carrier by way of example, the presentinvention is not limited thereto.

That is, a separate substrate (hereinafter, referred to as a supportsubstrate) rather than the carrier may also be used. A detaileddescription thereof will be provided below.

The semiconductor chips may be mounted on the support substrate, onwhich electrode patterns are formed, instead of the carrier. In thiscase, the separate adhesive layer 70 (See FIG. 3B) is not used unlike inthe case of the above-mentioned embodiment, and the respectivesemiconductor chips may be mounted on the support substrate while havingseparate connection pads directly bonded to the electrode patternsformed on the support substrate.

In addition, a support substrate on which circuit patterns or electrodepatterns are not formed may also be formed. In this case, thesemiconductor chips are mounted on and fixed to one surface of thesupport substrate, through holes are formed in the support substrate atpositions corresponding to positions at which the connection pads of thesemiconductor chips are disposed, and circuit patterns formed on theother surface of the support substrate are electrically connected to theconnection pads through the through holes.

Therefore, when the support substrate is used as described above, theprocess of removing the adhesive layer in the above-mentioned embodimentmay be omitted, and the support substrate may be directly formed as thesubstrate part. In addition, the substrate part may be formed as amulti-layer substrate by repeatedly forming new insulating layers andcircuit patterns on the outer surface of the support substrate asnecessary.

As set forth above, with the semiconductor package and the method ofmanufacturing the same according to the embodiments of the presentinvention, only good semiconductor chips are sorted among the individualsemiconductor chips and then rearranged to manufacture the semiconductorpackage, whereby reliability of a product may be secured.

In addition, a scheme of sealing the semiconductor chip to therebyprotect the semiconductor chip from the outside is used, whereby all ofsemiconductor chips having various forms such as a form of a flip chip,a form of a chip using a wire bonding scheme, or the like, may beutilized.

Further, the antenna part and the semiconductor chip are disposed at aposition adjacent to each other to be formed integrally with each other,whereby an electrical connection distance between the semiconductor chipand the antenna part may be minimized. Therefore, when the semiconductorpackage is used in the millimeter wave band (particularly, 60 GHz band),loss generated between the antenna part and the semiconductor chip maybe minimized.

Furthermore, the method of manufacturing a semiconductor packageaccording to the present embodiment forms the antenna part as well asthe substrate part during the process of forming the substrate part,whereby the number of manufacturing processes and a manufacturing costmay be reduced as compared to the case of the related art in which theantenna is separately manufactured and then coupled to the substratepart.

Further, the semiconductor manufacturing equipment according to therelated art is utilized, whereby new equipment investment formanufacturing the semiconductor package may be minimized. In addition,fine circuit patterns are formed on a substrate through thesemiconductor manufacturing process, whereby the semiconductor packagemay be miniaturized and thinned.

Furthermore, the sealing part is grinded to adjust a thickness of thesealing part, whereby characteristics of the antenna part may beadjusted. Therefore, signal matching of the antenna part may beperformed during a manufacturing process.

While the present invention has been shown and described in connectionwith the embodiments, it will be apparent to those skilled in the artthat modifications and variations can be made without departing from thespirit and scope of the invention as defined by the appended claims.

What is claimed is:
 1. A method of manufacturing a semiconductorpackage, the method comprising: disposing a plurality of semiconductorchips; forming a sealing part sealing the plurality of semiconductorchips; forming a substrate part on at least one surface of the sealingpart; and forming an antenna part on the sealing part or the substratepart.
 2. The method of claim 1, wherein the disposing of the pluralityof semiconductor chips includes arranging semiconductor chips sortedinto good products on a carrier.
 3. The method of claim 2, wherein thedisposing of the plurality of semiconductor chips includes attaching thesemiconductor chips to an adhesive layer formed on the carrier.
 4. Themethod of claim 1, wherein the forming of the sealing part includesforming the sealing part using an epoxy mold compound (EMC).
 5. Themethod of claim 1, further comprising, after the forming of the sealingpart, forming a via connection part penetrating through the sealingpart.
 6. The method of claim 5, wherein the forming of the antenna partincludes electrically connecting the antenna part and the semiconductorchips through the via connection part.
 7. The method of claim 1, whereinthe forming of the substrate part includes forming a multi-layersubstrate part on each of upper and lower surfaces of the sealing part.8. The method of claim 7, wherein the forming of the antenna partincludes forming a plurality of radiators on several layers of thesubstrate part.
 9. The method of claim 1, wherein the forming of theantenna part includes forming a groove in an outer surface of thesealing part and forming the antenna part therein.
 10. The method ofclaim 1, wherein the forming of the substrate part includes repeatedlyforming fine circuit patterns and insulating layers through asemiconductor manufacturing process